(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating small geometry dual-damascene structures while avoiding problems of surface coating, gap-fill and bubble formations.
(2) Description of the Prior Art
In fabricating very and ultra large scale integration (VLSI and ULSI) circuits, one of the more important aspects of this fabrication is the fabrication of metal interconnect lines and vias that provide the interconnection of integrated circuits in semiconductor devices. The invention specifically addresses the fabrication of conductive lines and vias using the damascene process. Using the dual damascene process, an insulating layer or a dielectric layer, such as silicon oxide, is patterned with a multiplicity of openings for the conductive lines and vias. The openings are simultaneously filled with a metal, such as aluminum, and serve to interconnect the active and/or the passive elements of an integrated circuit. The dual damascene process is also used for forming multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. The dual damascene process requires two masking steps to form first the via pattern after which the pattern for the conductive lines is formed. Critical to a good dual damascene structure is that the edges of the via openings in the lower half of the insulating layer are clearly defined. Furthermore, the alignment of the two masks is critical to assure that the pattern for the conductive lines aligns with the pattern of the vias. This requires a relatively large tolerance while the via may not extend over the full width of the conductive line.
Semiconductor device performance improvements are largely achieved by reducing device dimensions while increasing device-packaging densities. One of the major technologies that is used in the creation of semiconductor devices is photolithography. Photolithography is used to project images of device features that are contained in a reticle onto the surface where these images have to be created as device features. To obtain the required image quality and the subsequent high device yield, the images that are created in this manner must be precise and easy to repeat. This requirement of image precision brings with it that the light that is used to project the images is not deflected before reaching its target surface and not reflected upon reaching its target surface. Reflection of the projected light can occur if metal surfaces are underlying the target surface and if these metal surfaces readily reflect light. Unwanted reflections that are created by underlying layers of reflective materials are a prime source of distortion in the patterns that are created by photolithographic patterning.
To minimize the effect that reflected light has on image creation, Anti Reflective Coatings (ARC's) have been developed. These ARC's are frequently applied as a blanket deposition over the surface that caused light reflection such as a layer of metal. The coating of ARC however is an electrically conductive coating and can therefore only be applied where the application of this coating does not cause electrical short circuits between the layers over which the ARC is deposited. To prevent electrical short circuits from occurring, the ARC must be removed from between electrically conducting device features. This poses a problem for applications where dual damascene structures are being created. In the standard dual damascene process, an insulating layer is deposited over a semiconductor surface and coated with a layer of photoresist, the photoresist is exposed through a via mask with contains an image pattern of the via openings. The via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through an interconnect line pattern mask with an image pattern of conductive line openings. The second exposure of the interconnecting line patterns is aligned with the via mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. The metal is now polished back to form an inlaid planar dual damascene structure. The metal that is used to fill the dual damascene structure is never etched meaning that no layer of ARC can be deposited over the dual damascene structures since this would cause massive electrical shorts between the dual damascene structures through the layer of ARC.
The solution to the problem of electrical shorts that are created through the deposited layer of ARC is to find materials that have ARC properties that however are not electrically conductive, such as a typical dielectric material. Some dielectric ARC's, such as silicon rich silicon nitride or aluminum nitride, are known in the art. These dielectric ARC's however prove to be not suited for use as anti reflecting coatings because these materials exhibit the combination of ARC and insulating properties only at light frequencies in the Deep Ultra Violet 248 nm wavelength range. For most of the photolithographic exposures that are applied in the creation of small geometry device size features, such as I-line or G-line processing, these exposures are made in the higher wavelength (near ultra-violet or NUV with a wavelength of 365 nm) where the optimal ARC characteristics of these materials are not present.
Accordingly, there is a need for an improved semiconductor manufacturing operation which provides the action of an anti-reflective coating and that is applicable to the more prevalent I-line or G-line processing and which can be used in applications, such as dual damascene, which require ARC's that are nonconductive and that are potentially used as a damascene etch stop layer.
FIGS. 1a and 1b graphically illustrate the conventional process of the formation of a dual damascene structure.
FIG. 1a gives and overview of the sequence of steps required in forming a Prior Art dual damascene structure. The numbers referred to in the following description of the formation of the dual damascene structure relate to the cross section of the completed dual damascene structure that is shown in FIG. 1b.
FIG. 1a, 21 shows the creation of the bottom part of the dual damascene structure by forming a via pattern 22 on a surface 24, this surface 24 can be a semiconductor wafer but is not limited to such. The via pattern 22 is created in the plane of a dielectric layer 20 and forms the lower part of the dual Damascene structure. SiO.sub.2 can be used as a dielectric for layer 20.
FIG. 1a, 22 shows the deposition within plane 30 (FIG. 1b) of a layer of non-metallic material such as poly-silicon on top of the first dielectric 20 and across the vias 22, filling the via openings 22.
FIG. 1a, 23 shows the formation of the top section 41 of the dual damascene structure by forming a pattern 41 within the plane of the non-metallic layer 30. This pattern 41 mates with the pattern of the previously formed vias 22 (FIG. 1a, step 21) but it will be noted that the cross section of the opening 41 within the plane 30 of the non-metallic layer is considerably larger than the cross section of the via opening 22. After pattern 41 has been created and as part of this pattern creation step, the remainder of the non-metallic layer 30 is removed, the pattern 41 remains at this time.
FIG. 1a, 24 shows the deposition and planarization (down to the top surface of pattern 41) of an inter level dielectric (ILD) 50, a poly-silicon can be used for this dielectric.
FIG. 1a, 25 shows the creation of an opening by removing the poly-silicon from the pattern 41 and the via 22. It is apparent that this opening now has the shape of a T and that the sidewalls of the opening are not straight but show a top section that is larger than the bottom section.
FIG. 1a, 26 shows the step of filling the created opening 22/41 of the dual damascene structure with metal after which the metal is removed using CMP from the surface of layer 50 (FIG. 1b).
FIG. 1b shows the cross section of the dual Damascene structure where a barrier 70 has been formed on the sides of the created opening. The opening, which has previously been created by removing the poly-silicon from the pattern 41 and the vias 22, has been filled with a metal. Metal such as Wolfram or copper can be used for this latter processing step. The narrow lower section 22 of the dual damascene structure is frequently referred to as the via or contact section while the wider upper section 41 is frequently referred to as the trench or interconnect line section.
FIGS. 2, 3 and 4 show a Prior Art sequence of steps the are used to create a dual damascene structure using a layer of ARC.
FIG. 2 shows a cross section of the opening 70 that has been created through the two layers of dielectric 66 and 68. Layer 60 is a stop layer that has been deposited prior to the formation of the first layer of dielectric 66. Layer 60 of etch stop material is typically deposited to a thickness of 1700 Angstrom and can contain SiON. Layer 60 is the etch stop layer for etching the opening 70. Over layer 66 of dielectric a second stop layer 62 is deposited, also typically to a thickness of about 1700 Angstrom while this layer also can contain SiON. This stop layer 62 serves as the stop for the etching of the interconnect line pattern that forms the top section of the profile of the dual damascene structure. A second layer 68 of dielectric is deposited over the second stop layer 62. A final layer 64 is deposited over the surface of the second dielectric 68, this layer can contain SiON and serves as a stress relieve layer over the dielectric layer 68. The lower section (roughly below the top surface of the second stop layer 62) of opening 70 forms the plug or via section of the dual damascene structure, the upper section (roughly above the top surface of the second stop layer 62) needs to be widened (etched) in order to form the trench or interconnect pattern of the dual damascene structure. The stop layers 60, 62 and 64 of SiON can be formed to a thickness of about 1700 angstrom through a CMP method employing silane as a silicon source material and ammonia as a nitrogen source material.
FIG. 3, shows how, before the etch for the trench of the dual damascene structure takes place, an ARC layer 72 is deposited inside opening 70 and over the top surface of layer 64 of SION. This layer 72 serves the purpose that has been detailed above for the function of ARC layers. This layer 72 further serves the function of protecting the etch stop layer 60 at the bottom of this opening 70. The ARC layer 72 also allows, due to its protective nature, for a decrease in the thickness of layer 60 whereby layer 60 continues to serve as a stop layer during the first etch (to create the lower section of the dual damascene structure). The deposition of layer 72 of ARC further allows for a decrease in the thickness of the Inter Metal Dielectric (IMD) layer 68 thereby providing a level of control over the profile of the created opening of the dual damascene structure. Photoresist layer 74, deposited to a thickness of about 8000 Angstrom, forms a positive photoresist material and is deposited over the surface of layer 72 and patterned to created the trench profile of the dual damascene structure. The second layer of dielectric 68 can now be etched.
FIG. 4 shows a cross section after the latter etch has been completed. Critical dimension control of the dual damascene profile requires that all angles of corners and contours of the dual damascene are 90-degree angles.
U.S. Pat. No. 5,877,076 (Dai), U.S. Pat. No. 5,741,626 (Jain) and U.S. Pat. No. 5,882,996 (Dai) show dual damascene processes using BARC layers.
U.S. Pat. No. 5,874,201 (Licata et al.) shows a dual damascene with an organic layer.